Sunday, March 6, 2011

Wonderful Opportunities for Physical Design & CAD Professionals with World's leading Chip Design Company



(1)Physical Design Engineer

Position: SDE/MTS and above
Positions Open: Multiple
Minimum Exp: 5 years with M.tech or 7+ years preferred


Key Responsibilities:


The position is for a Physical Design Engineer in the PD group catering to building the next generation fusion SoCs and discrete graphics processors. Fusion programs cater to the next gen compute requirements bringing in CPU, GPU and other functions on an integrated monolithic die. This position requires interface with large front-end design teams in US, Canada, Shanghai and India, mentoring new hires and owing an entire chip or portion of the chip from RTL/gates to tapeout. 


The Physical Design Engineer will be responsible for 1. full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks, low power solution development etc. In addition to this, he/she will also be participating in Physical design flow development/upgrade by continuously working with internal design teams and CAD vendors.


Job Requirements:
Understanding Verilog HDL
Understanding Deep Submicron effects such as 90nm and below
Understanding OCV, DFM, DFY
Excellent Block level and Full-chip physical design skills
Self-motivated, leadership skills and experience working with global  teams
Minimum 5 years of ASIC physical design experience
Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc
Hands on experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools
Should have participated in a minimum of 3 fullchip tapeouts.


Mail your profiles at cvs@cinsolutions.co.in ASAP with the subject line as Years of Experience/ PDE / Current Organisation in order.


(2)Physical Design Manager


Positions Open: Multiple
Minimum Exp: 10 years (3+ years management preferred)


Key Responsibilities:


The Physical Design Manager will be responsible for the planning and execution of all SoC or IP physical design activities for next generation products.  She/he will be responsible for execution of Physical Design (place and route) duties both at block level, IP/macro level, as well as chip-level. This includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Logical vs. Schematic (LVS) checks.
The candidate will:
·         Provide technical direction, mentoring, skill development
·         Be a forward thinker to improve process and innovation
·         Interface with other local and global front end and Physical Design Managers/Directors to define schedules, resource requirements etc.,
·         Provide leadership and direction in crisis
·         Interface with front-end ASIC teams to resolve issues and problems
·         Responsible for execution of program. Multiple projects on the go.

In addition, strong communication skills and an ability to work in large groups are essential to being successful.  Insight into multi-site project development will be an asset.
The following aspects are desirable:


Technical :
Understanding Verilog HDL
Understanding Deep Submicron effects such as 90nm and below
Understanding OCV, DFM, DFY
Excellent Block level and Full-chip physical design skills
Back ground of all aspects of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc
Hands on recent or past experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools
Understanding of complete SoC development cycle, from architecture to post-silicon debug preferred
Should have participated in a minimum of 3 fullchip tapeouts.


Management :
Minimum 3 years of ASIC physical design management experience, working with global teams
Self-motivated, conflict resolution skills, and experience working with global  teams across time zones
Detail oriented and schedule driven
People management skills as well as technical project management skills




Mail your profiles at cvs@cinsolutions.co.in ASAP with the subject line as Years of Experience/ PDM / Current Organisation in order.



(3)CAD

Position: SDE/MTS and above with corresponding title (MTS, Master + 9-10 years)
Years of experience: 6-10 (with B. Tech/M.Tech)


Key Responsibilities:



  • Strong in programming in PERL, Python. Developed flows/tools and methodologies for SoC designs. Has very good experience in supporting automation or methodology development for low power designs. Strong understanding of end to end SoC Design flow.
  • Very good communication skills; should have worked in cross-site environments


Skills:
a)      Very strong programming skills in PERL, Tcl and/or Python
b)      Strong knowledge of Design flow (PD)
c)       Very good understanding of LEF, LIB, SPEF, DEF, Verilog formats
d)      From EDA companies, folks who do second level design support are the ones to look out.



Mail your profiles at cvs@cinsolutions.co.in ASAP with the subject line as Years of Experience/ CAD / Current Organisation in order.

1 comment:

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